Staff/ Sr. Staff Design Verification Engineer - QGOV

Job Description

<p><h3><b>Company:</b></h3>
<p>Qualcomm Technologies, Inc.</p>
<h3><b>Job Area:</b></h3>
<p>Engineering Group, Engineering Group > ASICS Engineering</p>
<h3><b>General Summary:</b></h3>
<p>Design Verification</p>
<h3><b>Role:</b></h3>
<ul>
<li>Familiarity with RTL design in Verilog and SystemVerilog</li>
<li>Develop verification methodology, ensuring a scalable and portable environment across simulation and emulation.</li>
<li>Develop test plan to verify hardware building blocks, design macros and standard interfaces (PCIE, DDR, USB, I2C, SPI, etc).</li>
<li>Own end-to-end DV tasks from coding test benches and test cases, write assertions, run simulations, and achieve all coverage goals.</li>
<li>Explore innovative DV methodologies (formal, simulation, and emulation based) to continuously push the quality and efficiency of test benches.</li>
<li>Develop and maintain an emulation environment to collect metrics related to emulation.</li>
</ul>
<p><b>Need to be in San Diego full time, 5 days a week</b></p>
<p><b>Applicants selected will be subject to a government security investigation and must meet eligibility requirements for access to classified information.</b></p>
<p><b>Must be a U.S. citizen and eligible to receive a U.S. Government security clearance.</b></p>
<h3><b>Required Qualifications:</b></h3>
<ul>
<li>5+ years of work experience with RTL/FPGA design (Verilog), embedded system architecture.</li>
<li>5+ years of Design Verification, Emulation and Debug experience with simulation, emulation and prototyping flows.</li>
</ul>
<p><b>Relevant experience of 5+ yrs in any of the mentioned domain - Design/Verification/ Implementation.</b></p>
<h3><b>Preferred Qualifications:</b></h3>
<ul>
<li>Knowledge of communication protocols such as AXI4-x, DDRx, PCIe, etc.</li>
<li>Strong SystemVerilog/UVM based verification skills & experience with assertion & coverage-based verification methodology.</li>
<li>Good understanding of chip-level functional model building.</li>
<li>Good understanding of OOP concepts and experience in HVL such as System Verilog, UVM/OVM & System C.</li>
<li>Knowledge of behavioral and structural models and familiarity with simulation environments.</li>
<li>Experience customizing and debugging make-based build flows and working with Xilinx’s Vivado tools.</li>
<li>Experience with cm tools such as Git and Gerrit.</li>
<li>Experience with formal/static verification methodologies will be a plus.</li>
<li>Experience with emulation platforms – Palladium, Zebu, Veloce, FPGAs.</li>
<li>Experience with synthesizing and optimizing designs and verification components developed in synthesizable Verilog.</li>
<li>Experience with C/C++ DPI transactors and monitors.</li>
<li>Develop and maintain emulation environment to collect metrics related to emulation.</li>
<li>Develop environment to run verification test cases, OS boot, performance benchmarks and other vectors.</li>
<li>Design, develop, and maintain CAD infrastructure for silicon design teams enabling bring up, test and debug automations.</li>
<li>Execute verification plans, including design bring-up, DV environment bring-up, regression enabling for all features under your care, debug of the test failures.</li>
<li>Experience with debugging tools such as JTAG and lab test equipment such as logic analyzers, oscilloscopes, signal generators, etc.</li>
<li>Experience with GLS, and scripting languages such as Perl, Python is a plus.</li>
<li>Linux OS proficiency.</li>
</ul>
<p>The ideal candidate would be a self‑starter with strong initiative, discipline, motivation, and a focus on quality.</p>
<p>The candidate must be a team player and be flexible and open to a variety of task assignments within the team.</p>
<h3><b>Minimum Qualifications:</b></h3>
<ul>
<li>Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.</li>
<li>Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.</li>
<li>PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.</li>
</ul>
<p><b>Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities.</b></p>
<p><b>Pay range: </b>$164,000.00 - $246,000.00</p>
<p>The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. In addition, Qualcomm offers a competitive annual discretionary bonus program, opportunities for annual RSU grants, and a highly competitive benefits package. For more details about our US benefits, please refer to the link below.</p>
<p>If you would like more information about this role, please contact Qualcomm Careers.</p>
</p>
#J-18808-Ljbffr